1. Field of the Invention
The present invention relates to a phase change memory cell with ovonic threshold switch selector with reduced dimensions and to the manufacturing method thereof.
2. Description of the Related Art
As is known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases are hence associated to resistivities of considerably different values.
Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.
In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.
Phase change can be obtained by locally increasing the temperature. Below 150° C., both the phases are stable. Starting from an amorphous state, and rising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide.
Memory devices exploiting the properties of chalcogenic materials (also called phase change memory devices) have been already proposed.
In a phase change memory including chalcogenic elements as a storage element, memory cells are arranged in rows and columns to form an array, as shown in FIG. 1. The memory array 1 of FIG. 1 comprises a plurality of memory cells 2, each including a memory element 3 of the phase change type and a selection element 4 interposed at cross-points of rows 6 (also called word lines) and columns 5 (also called bit lines).
In each memory cell 2, the memory element 3 has a first terminal connected to an own wordline 6 and a second terminal connected to a first terminal of an own selection element 4. The selection element 4 has a second terminal connected a bitline 5. In another solution, the memory element 3 and the selection element 4 of each cell 2 may be exchanged in position.
The composition of chalcogenides suitable for the use in a phase change memory device and a possible structure of a phase change element are disclosed in a number of documents (see, e.g., U.S. Pat. No. 5,825,046).
The selection element 4 may be implemented by any switching device, such as a PN diode, a bipolar junction transistor or a MOS transistor.
For example, U.S. Pat. No. 5,912,839 describes a universal memory element using chalcogenides and including a diode as a switching element. The diode may comprise a thin film such as polycrystalline silicon or other materials.
GB-A-1 296 712 and U.S. Pat. No. 3,573,757 disclose a binary memory formed by an array of cells including a switch element called “ovonic threshold switch” (also referred to as an OTS hereinafter), connected in series with a memory element called “ovonic memory switch” (OMS). The OTS and the OMS are formed adjacent to each other on an insulating substrate and are connected to each other through a conducting strip. Each cell is coupled between a row and a column of a memory array and the OTS has the same function as the selection element 4 in FIG. 1.
The OMS is formed by a chalcogenic semiconductor material having two distinct metastable phases (crystalline and amorphous) having different resistivities, while the OTS is built with a chalcogenic semiconductor material having one single phase (generally amorphous, but sometimes crystalline) with two distinct regions of operation having different resistivities. If the OTS and the OMS have substantially different high resistances, namely with the OTS having a higher resistance than the OMS, when a memory cell is to read, a voltage drop is applied to the cell that is insufficient to trigger the OMS when the latter is in its high resistance condition (associated with a digital “0” state), but is sufficient to drive the OTS in its low resistance condition when the OMS is already in its low resistance condition (associated with a digital “1” state).
OTS (see, e.g., U.S. Pat. No. 3,271,591, describing its use in connection with memory elements of the change phase type) have the characteristic shown in FIG. 2. An OTS has a high resistance for voltages below a threshold value Vth; when the applied voltage exceeds the threshold value Vth, the switch begins to conduct at a substantial constant, low voltage and presents a low impedance. When the current through the OTS falls below a holding current IH, the OTS goes back to its high-impedance condition. This behavior is symmetrical and-occurs also for negative voltages and currents.
As discussed in U.S. Pat. No. 6,816,404, in the name of STMicroelectronics S.r.I. and Ovonyx Inc., a memory element of a phase change memory device comprises a chalcogenic material and a resistive electrode, also called heater.
In fact, from an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect.
In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), it is necessary to apply a voltage/current pulse of a suitable length and amplitude and allow the chalcogenic material to cool slowly. In this condition, the chalcogenic material changes its state and switches from a high resistivity to a low resistivity state (also called the set state).
Vice versa, when the chalcogenic material is in the set state, it is necessary to apply a voltage/current pulse of suitable length and high amplitude so as to cause the chalcogenic material to switch to the amorphous phase.
According to U.S. Pat. No. 6,816,404, to reduce the amount of current needed to cause the chalcogenic material to change its state, the heater is formed by a wall structure obtained by depositing a suitable resistive material. Furthermore, the chalcogenic material includes a thin portion extending transversely to the wall structure, so as to obtain a small contact area. Here, the selection element is implemented by a bipolar junction diode formed in a semiconductor substrate just below the memory element.
However, known OTS suffer from current leakage in the amorphous (reset) state, which correspond to an open-switch configuration. Although the OTS chalcogenic layer has high resistivity, in fact, a substantial amount of current flows when a voltage is applied across the OTS, thereby resulting in an undesired power consumption.